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PROGRAM
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Technical Program (DRAFT) |
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The technical program may be subject to changes
Monday, 4/14/14
7:30 - 8:30 Registration & Breakfast - SW Foyer
8:30 - 10:30 Plenary Session - Silverado East
- Welcome Message
C. Thibeault (E. Tech. Sup. Montreal), General Chair
- Program Introduction
Y. Makris (University of Texas at Dallas), Program Chair
- Opening Keynote: Test Is It, Or Is It Not, Value Added and What Does That Mean to the Future of Test Engineers? Read more...
Arthur (Art) L. George (Senior Vice-President and Manager, Analog Engineering Operations, Texas Instruments)
- Invited Keynote: Implications for Test of Modular Electronic Products Read more...
Kaigham J. Gabriel (Advanced Technology & Projects, Google)
- Awards Presentation
Y. Zorian (Synopsys), Ex-Officio
10:30 - 11:00 Break
11:00 - 12:00 Sessions 1
Session 1A: Fault Simulation & Defect Coverage (Sterling)
Moderator: Hans-Joachim Wunderlich (University of Stuttgart)
- Fault Simulation With Test Switching for Static Test Compaction (Best Paper Award Candidate)
Irith Pomeranz (Purdue University)
- Fast Evaluation of Test Vector Sets Using a Simulation-based Statistical Metric
Shahrzad Mirkhani, Jacob Abraham (University of Texas at Austin)
- Improving CMOS Open Defect Coverage Using Hazard Activated Tests
Chao Han, Adit Singh (Auburn University)
Session 1B: Analytical Methods in Analog Test (Joseph Phelps)
Moderator: Senthil Arasu Thirunavukarasu (Broadcom)
- Efficient Monte Carlo-Based Analog Parametric Fault Modelling
Haralampos Stratigopoulos (TIMA Laboratory/CNRS), Stephen Sunter (Mentor Graphics)
- A Method for Phase Noise Extraction from Data Communication
Allan Ecker, Mani Soma (University of Washington)
- Accurate and Efficient Method of Jitter and Noise Separation and Its Application to ADC Testing
Li Xu, Degang Chen (Iowa State University)
IP Session 1C: Existing/Emerging Low Power Techniques (Chappellet/Robert Mondavi)
Organizers & Moderators: Charutosh Dixit and Ramesh Tekumalla (LSI)
- Fast Power Analysis for Digital Test Vectors
Wei Zhao (Cisco)
- Power-aware Embedded Scan Test
Nilanjan Mukherjee (Mentor Graphics)
- Power Management Handling and Test Generation
Vivek Chickermane (Cadence)
12:00 - 13:20 Lunch
13:20 - 14:20 Sessions 2
Session 2A: Memory Test & Repair (Sterling)
Moderator: Haluk Konuk (Broadcom)
- Testing Methods for a Write-Assist Disturbance-Free Dual-Port SRAM (Best paper Award Candidate)
Hao-Yu Yang, Chen-Wei Lin, Chao-Ying Huang, Ching-Ho Lu, Chen-An Lai, Mango Chao (National Chiao Tung University,) Rei-Fu Huang (MediaTek)
- Built-In Self-Test Methodology for Diagnosis of Backend Wearout Mechanisms in SRAM Cells
Woongrae Kim, Linda Milor (Georgia Institute of Technology)
- Fault Modeling and Test Algorithm Creation Strategy for FinFET-Based Memories
Gurgen Harutyunyan, Grigor Tshagharyan, Valery Vardanian, Yervant Zorian (Synopsys)
New Topic Session 2B: Co-Design and Reliability of Power Electronic Modules - Current Status and Future Challenges (Joseph Phelps)
Organizers: Bozena Kaminska (Simon Fraser University) & Bernard Courtois (CMP)
Moderator: Bernard Courtois (CMP)
Presenter: Christopher Bailey (University of Greenwich)
IP Session 2C: Advances in Yield Learning (Chappellet/Robert Mondavi)
Organizer & Moderator: Yen-Tzu Lin (Nvidia)
- Scan Based Yield Learning Challenges in the FinFET Era
Brady Benware (Mentor Graphics)
- Leveraging Equipment Data for Better Yield Learning
Brian Stine (PDF Solutions)
- Statistical Metrology Opportunities at User Application Frequencies and their Impact on SRAM Technology Development, VMIN Characterization and SoC Time-to-market
Azeez Bhavnagarwala (ARM)
14:20 - 14:40 Break
14:40 - 15:40 Sessions 3
Session 3A:Testing of Power Electronics & Silicon TV Tuners (Sterling)
Moderator: Dongsheng (Brian) Ma (UT Dallas)
- A Built-In Self-Test Technique for Load Inductance and Lossless Current Sensing of DC-DC Converters (Best Paper Award Candidate)
Tao Liu, Chao Fu, Sule Ozev, Bertan Bakkaloglu (Arizona State University)
- Alternative "Safe" Test of Hysteretic Power Converters
Xian Wang (Georgia Institute of Technology), Kenfact Blanchard, Silva Estella (Texas Instruments), Abhijit Chatterjee (Georgia Institute of Technology)
- Accelerating Capture of Infrequent Errors on ATE for Silicon TV Tuners
Yongquan Fan, Anant Verma, Dave Trager, Ramin Poorfard, John Janney, Sandeep Kumar (Silicon Labs)
Session 3B: Thermal,Self-Test & Error Detection (Joseph Phelps)
Moderator: Lorena Anghel (TIMA Lab)
- Self-Heating Thermal-Aware Testing of FPGAs
Abdulazim Amouri, Jochen Hepp, Mehdi Tahoori (Karlsruhe Institute of Technology)
- Structural Software-Based Self-Test of Networks-on-Chip
Atefe Dalirsani, Michael Imhof, Hans-Joachim Wunderlich (University of Stuttgart)
- Accelerated Online Error Detection in Many Core Microprocessor Architectures
Manolis Kaliorakis, Nikos Foutris, Dimitris Gizopoulos (University of Athens), Mihalis Psarakis (University of Piraeus)
IP Session 3C: Solving Today's Test Challenges (Chappellet/Robert Mondavi)
Organizer & Moderator: John Kim (Synopsys)
- High-Observability Pattern Generation for Better PFA Isolation During Yield Learning
Wolfgang Meyer (Synopsys)
- Test Vehicles for 2.5/3D Die Stacking
T.M. Mak (GlobalFoundries)
- Expanding Scope and Architectural Convergence of Chip Pervasive Logic
Amitava Majumdar (Xilinx)
15:40 - 16:00 Break
16:00 - 17:30 Sessions 4
Special Session 4A: Elevator Talks (Sterling)
Organizer & Moderator: Jennifer Dworak (SMU)
- DPPM for Analog and RF Circuits
Vishwani Agrawal (Auburn University)
- Major Challenges for the On-line Self-Test of Embedded Processors through Functional Programs
Paolo Bernardi (Politecnico di Torino)
- Trustworthy SoC Architecture with On-demand Security Policies and HW-SW Cooperation
Yier Jin (University of Central Florida)
- Analog/RF Test Problem Solving with Statistically Sampled Data
Salvador Mir (TIMA Lab)
- Dealing with the Physical Issues at the System Level
Zain Navabi (WPI)
- Power Supply Analysis for Reliability and Security
Chintan Patel (UMBC)
- Application and Algorithm Aware Approaches to Fixing Hardware Faults
Joseph Sloan (UT Dallas)
- Wireless Testing with Inductive Coupling
Danella Zhao (University of Louisiana at Lafayette)
Panel Session 4B: Testing and Calibration for Power Management Circuits (Joseph Phelps)
Organizer: Sule Ozev and Bertan Bakkaloglu (ASU)
Moderator: Sule Ozev (ASU)
Panelists:
- Omar Sawalha (Maxim)
- Rubin Parekhji (Texas Instruments)
- Dongsheng (Brian) Ma (UT Dallas)
- Bertan Bakkaloglu (ASU)
- Scott Benner (Qualcomm)
IP Session 4C: Disruptive Solutions in the Non-Digital World (Chappellet/Robert Mondavi)
Organizers: Amitava Majumdar (Xilinx) and Suriya Natarajan (Intel)
Moderator: Amitava Majumdar (Xilinx)
- A Realistic Analog-equivalent to the Digital Stuck-at Model
Stephen Sunter (Mentor Graphics)
- Defining a DFX Strategy for Analog, HSIO, and Mixed-signal IP in SoCs
Prashant Goteti (Intel)
- Accelerating IC Laser Trimming through Wafer-Level Spatial Correlation Modeling
Ke Huang (UT Dallas)
Tuesday, 4/15/14
7:30 - 8:30 Registration & Breakfast (SW Foyer)
8:30 - 9:30 Sessions 5
Session 5A: Emerging Technologies & Microfluidics (Hans Kornell)
Moderator: Jun Qian (AMD)
- Test Generation and Design-for-Testability for Flow-Based mVLSI Microfluidic Biochips (Best Paper Award Candidate)
Kai Hu (Duke University), Tsung-Yi Ho (National Cheng Kung University), Krishnendu Chakrabarty (Duke University)
- Fault Tolerant Nanoarray Circuits: Automatic Design and Verification
Pasquale Ranone, Giovanna Turvani, Fabrizio Riente, Graziano Mariagrazia, Maurizio Zamboni, Massimo Ruo Roch (Politecnico di Torino)
- Detection, Diagnosis, and Repair of Faults in Memristor-based Memories
Sachhidh Kannan (NYU Abu-Dhabi), Naghmeh Karimi, Ramesh Karri (Polytechnic Institute of NYU), Ozgur Sinanoglu (NYU Abu-Dhabi)
Session 5B: 3D IC Test - I (Freemark Abbey)
Moderator: Kazumi Hatayama (NAIST)
- Quality versus Cost Analysis for 3D Stacked ICs
Mottaqiallah Taouil, Said Hamdioui (Delft University of Technology), Erik Jan Marinissen (IMEC)
- Test Planning and Test Access Mechanism Design for Stacked Chips Using ILP
Breeta Sengupta, Erik Larsson (Lund University)
- Modeling Location Based Wafer Die Yield Variation in Estimating 3D Stacked IC Yield from Wafer to Wafer Stacking
Eshan Singh (Intel)
IP Session 5C: Machine Learning and Data Analysis in Test (Chappellet/Robert Mondavi)
Organizers & Moderators: Sounil Biswas (Nvidia)
- Learning from Test Data
John Carulli (Texas Instruments)
- Test Data Assembly and Processing for Rapid Predictive Analytics Enabling Yield Improvement and Cost Savings
Dragoljub Drmanac (Intel)
- Effective Workflow for Fault Localization in Volume Diagnostics to PFA Flow
Arpan Bhattacherjee (Synopsys)
9:30 - 9:50 Break
9:50 - 10:50 Sessions 6
Session 6A: High-Speed I/O Testing and Aging (Hans Kornell)
Moderator: Chintan Patel (UMBC)
- SMV Methodology Enhancements for High Speed I/O Links of SoCs (Best Paper Award Candidate)
Andres Viveros Wacher, Ricardo Alejos, Liliana Alvarez De La Cruz, Israel Diaz Castro, Brenda Marcial Camacho, Gaston Motola Acuna, Edgar Vega (Intel)
- Multi-channel Testing Architecture for High-speed Eye-diagram Using Pin Electronics and Subsampling Monobit Reconstruction Algorithms
Thomas Moon, Hyun Choi, David Keezer, Abhijit Chatterjee (Georgia Institute of Technology)
- Extraction of Threshold Voltage Degradation Modeling Due to Negative Bias Temperature Instability in Circuits With I/O Measurements
Soonyoung Cha, Chang-Chih Chen, Taizhi Liu, Linda Milor (Georgia Institute of Technology)
Session 6B: 3D IC Test - II (Freemark Abbey)
Moderator: Said Hamdioui (Delft University of Technology)
- At-Speed Interconnect Testing and Test-Path Optimization for 2.5D ICs
Ran Wang, Krishnendu Chakrabarty (Duke University), Sudipta Bhawmik (Qualcomm)
- Built-In Self-Test for Manufacturing TSV Defects before Bonding
Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre, Hakim Zimouche (LIRMM)
- TSV Aware Timing Analysis in Paths With Multiple TSVs
Carolina Metzler, Aida Todri-Sanial, Alberto Bosio, Luigi Dilillo, Patrick Girard, Arnaud Virazel (LIRMM)
Embedded Tutorial Session 6C: Unstructured Text: Test Analysis Techniques Applied to Non-Test Problems (Chappellet/Robert Mondavi)
Organizer: Yiorgos Makris (UT Dallas)
Moderator: Ronald (Shawn) Blanton (CMU)
Presenter: Anne Gattiker (IBM)
10:50 - 11:10 Break
11:10 - 12:10 Sessions 7
Session 7A: Built-in Monitoring & Calibration in RF ICs (Hans Kornell)
Moderator: Haralampos Stratigopoulos (TIMA Lab)
- Reliability Enhancement Using in-field Monitoring and Recovery for RF Circuits
Doohwang Chang, Sule Ozev, Bertan Bakkaloglu, Sayfe Kiaei (Arizona State University), Engin Afacan, Gunhan Dundar (Bogazici University)
- Continuous Wave Radar Circuitry Testing Using OFDM Technique
Mohamed Metwally, Nicholai L'Esperance, Tian Xia (University of Vermont), Mustapha Slamani (IBM)
- A Built-in Gain Calibration Technique for RF Low-Noise Amplifiers
Ya-Ru Wu, Yi-Keng Hsieh, Po-Chih Ku, Liang-Hung Lu (National Taiwan University)
New Topic Session 7B: Challenges and Opportunities in Test and Design for Test (DFT) of MEMS Sensors (Freemark Abbey )
Organizers: B. Courtois (CMP) & B. Kaminska (SFU)
Moderator: Bozena Kaminska (Simon Fraser University)
Presenter: Mary Ann Maher (SoftMEMS LLC)
IP Session 7C: Reduced Pin-count Testing - How Low Can We Go? (Chappellet/Robert Mondavi)
Organizer & Moderator: Stephen Sunter (Mentor Graphics)
- Reduced Pin-Count Final Test of MCUs
Steve Comen (Texas Instruments)
- Programmable Analog SoC RPC Test Approaches for x64 Parallelism
Paul Berndt (Cypress Semiconductor)
- Addressing Challenges in Reduced Pin-Count Test Scenarios for DDR and PCIE
Ram Rajamani (Intel)
12:10 - 13:30 Lunch
13:30 - 15:00 Sessions 8
Special Session 8A: E.J. McCluskey Doctoral Thesis Competition (Presentations & Posters) (Hans Kornell)
Organizers: Michele Portolan (Polytechnic Institute of Grenoble) & Michail Maniatakos (NYU Abu Dhabi)
Moderator: Michail Maniatakos (NYU Abu Dhabi)
Contestants:
- Nikos Foutris (University of Athens)
- Subhadip Kundu (IIT Kharagpur)
- Sukeshwar Kannan (University of Alabama)
- Praveen Venkataramani (Auburn University)
- Samah Saeed (NYU Abu Dhabi)
- Sendil Arasu (University of Texas at Dallas)
- Vaneet Singh (IIT Delhi)
Panel Session 8B: In-field Testing of SoC Devices: Which Solutions by Which Players? (Freemark Abbey)
Organizers & Moderators: : Matteo Sonza-Rorda (Politecnico di Torino) and Dimitris Gizopoulos (University of Athens)
Panelists:
- Janusz Rajski (Mentor Graphics)
- Jacob Abraham (UT Austin)
- Teresa McLaurin (ARM)
- Xinli Gu (Huawei)
- Paul Ryan (Intel)
Hot Topic Session 8C: Designers' and Test Researchers' Roles in Analog DFT (Chappellet/Robert Mondavi)
Organizer: Masahiro Ishida (Advantest)
Moderator: Takahiro Yamaguchi (Advantest)
Presenters:
- Analog Design-for-Test vs. Analog Designs: The Missing Link
Mani Soma (University of Washington)
- Is an Integrated Test and Design Approach Realistic for Analog and Mixed-Signal ICs?
Terri Fiez (Oregon State University)
- Analog and High-Speed I/O DFV and DFM at Nano-Scales
Mike Peng Li (Altera Corporation)
15:00 - 15:30 Break
15:30 - 22:00 Social Event
Wednesday, 4/16/14
7:30 - 8:30 Registration & Breakfast (SW Foyer)
8:30 - 9:30 Sessions 9
Session 9A: Delay, Power & Performance Issues in Test (Hans Kornell)
Moderator: Prab Varma (Ansys)
- Identification of Testable Representative Paths for Low-Cost Verification of Circuit Performance During Manufacturing Tests and In-Field Tests
Jifeng Chen (University of Connecticut), LeRoy Winemberg (Freescale Semiconductor), Mohammad Tehranipoor (University of Connecticut)
- Power/Ground Supply Voltage Variation-Aware Delay Test Pattern Generation
Lu Wang, Xutao Wang, Milad Maleki, Bao Liu (University of Texas at San Antonio)
- Improved Power Supply Noise Control for Pseudo Functional Test
Tengteng Zhang, Duncan Walker (Texas A&M University)
Session 9B: Analog/MS/RF Test Medley (Freemark Abbey)
Moderator: Linda Milor (Georgia Institute of Technology)
- Phase-Locked Loop Design with SPO Detection and Charge Pump Trimming for Reference Spur Suppression
Sen-Wen Hsiao (Georgia Institute of Technology), Chung-Chun Chen, Randy Caplan, Jeff Galloway, Blake Gray (Silicon Creations), Abhijit Chatterjee (Georgia Institute of Technology)
- Development and Empirical Verification of an Accuracy Model for the Power Down Leakage Tests
Jae Woong Jeong, Sule Ozev (Arizona State University), Friedrich Taenzler, Jane Chao (Texas Instruments)
- A 4-GHz Universal High-Frequency On-Chip Testing Platform for an IP Validation
Ping-Lin Yang, Cheng-Chung Lin, Ming-Zhang Kuo, Sang-Hoo Dhong, Chien-Min Lin, Kevin Huang, Ching-Nen Peng, Min-Jer Wang (TSMC)
Hot Topic Session 9C: Test and Fault Tolerance for Emerging Memory Technologies (Chappellet/Robert Mondavi)
Organizers: Suriya Natarajan (Intel) and Amitava Majumdar (Xilinx)
Moderator: Jeyavijayan Rajendran (Polytechnic Institute of NYU)
- Embedded Spin Transfer Torque RAM: New Frontiers in Design & Test
Arijit Roychowdhury (Georgia Institute of Technology)
- Test Considerations with TSV Stacked Memory
David Zimmerman (Intel)
- Building Reliability in Flash Memories
Manuel D'Abreu (SanDisk)
9:30 - 9:50 Break
9:50 - 10:50 Sessions 10
Session 10A: Diagnosis (Hans Kornell)
Moderator: Naghmeh Karimi (Polytechnic Institute of NYU)
- A Shared Memory Based Parallel Diagnosis System
Xiaolei Cai, Emil Gizdarski, Dan Landau (Synopsys)
- An Efficient Diagnosis Method to Deal With Multiple Fault Pairs Simultaneously Using a Single Circuit Model
Cheng-Hung Wu, Kuen Jong Lee, Wei-Cheng Lien (National Cheng Kung University)
- Atomic Model Learning: A Machine Learning Paradigm for Post Silicon Debug of RF/Analog Circuits
Sabyasachi Deyati, Barry Muldrey, Aritra Banerjee, Abhijit Chatterjee (Georgia Institute of Technology)
Session 10B: Hardware Security (Freemark Abbey)
Moderator: Ozgur Sinanoglu (NYU Abu-Dhabi)
- Functional Block Extraction for Hardware Security Detection Using Time-Integrated and Time-Resolved Emission Measurements
Franco Stellari, Peilin Song, Herschel Ainspan (IBM)
- Active Defense against Counterfeiting Attacks through Robust Antifuse-based On-Chip Locks
Abhishek Basak, Yu Zheng, Swarup Bhunia (Case Western Reserve University)
- Auto-identification of Positive Feedback Loops in Multi-state Vulnerable Circuits
Zhiqiang Liu, You Li, Randall Geiger, Degang Chen (Iowa State University)
IP Session 10C: Advances in DFT and Compression (Chappellet/Robert Mondavi)
Organizer: Rohit Kapur (Synopsys)
Moderator: Irith Pomeranz (Purdue University)
- DFT to Enable Right Test Cost and Test Quality Tradeoffs in SOCs for Different End Applications
Rubin Parekhji (Texas Instruments)
- Using DFT Xtolerance Modes to Improve Diagnosability
Cy Hay (Synopsys)
- A Modular IP Flow for Extreme Compression
Jon Colburn (Nvidia)
10:50 - 11:10 Break
11:10 - 12:10 Sessions 11
Session 11A: Multi-Cycle, SoC & Voltage-Droop Test (Hans Kornell)
Moderator: Xinli Gu (Huawei)
- On the Use of Multi-Cycle Tests for Storage of Two-Cycle Broadside Tests
Irith Pomeranz (Purdue University)
- Test-Time Optimization in NOC-Based Manycore SOCs Using Multicast Routing
Mukesh Agrawal, Krishnendu Chakrabarty (Duke University)
- On-Chip Voltage-Droop Prediction Using Support-Vector Machines
Fangming Ye (Duke University), Farshad Firouzi (Karlsruhe Institute of Technology), Yang Yang, Krishnendu Chakrabarty (Duke University), Mehdi Tahoori (Karlsruhe Institute of Technology)
Special Session 11B: ITRS Adaptive Test Update (Freemark Abbey)
Organizer & Moderator: John Carulli (Texas Instruments)
- ITRS Adaptive Test Update Review
Phil Nigh (IBM)
- eXtended Adaptive Test (XAT): Blazing New Trails or Stuck in the Mud?
William Eklow (Cisco)
- What's in your ECID Scratch Pad???
Kevin Tiernan (Texas Instruments)
Special Session 11C: Young Professionals in Test (Elevator Talks) (Chappellet/Robert Mondavi)
Organizers: Alodeep Sanyal (Intel) and Yanjing Li (Intel)
Moderator: Alodeep Sanyal (Intel)
- Malicious Aging Acceleration in Processors
Naghmeh Karimi (Polytechnic Institute of NYU)
- RF Built-In Test with Non-Intrusive Sensors
Haralampos Stratigopoulos (TIMA Lab)
- Detecting Hardware Trojans with Self-Reference Timing Tests
Eshan Singh (Intel)
- An exploration of vector-based integer arithmetic on Intel Xeon Phi SIMD Extensions
Michail Maniatakos (NYU Abu Dhabi)
- Advanced Process Bring Up
Sounil Biswas (Nvidia)
12:10 - 13:30 Lunch
13:30 - 15:00 Sessions 12
Special Session 12A: Hot Topic: Split Manufacturing - IARPA's TIC program (Hans Kornell)
Organizers: Dean Collins (DRC Consulting LLC) and Ramesh Karri (Polytechnic Institute of NYU)
Moderator: Dean Collins (DRC Consulting LLC)
Presenters:
- IARPA Trusted Integrated Chips (TIC) Program in Split Manufacturing
Dean Collins (DRC Consulting LLC)
- Trusted Integrated Chips with Split Manufacturing Fabrication and Heterogeneous Integration at Northrop Grumman Aerospace Systems
Yeat Yang (NGC)
- Security Implications of Split Manufacturing
Jeyavijayan Rajendran (Polytechnic Institute of NYU)
- Split-fabrication Mechanics, Testing, and Issues Concerning Obscuring
Mike Bajura (ISI)
Special Session 12B: Hot Topic: Stay Relevant with Standards-based DFT (Freemark Abbey)
Organizers: Bruce Cory (Nvidia)
Moderator: Victor Champac (INAOE)
- Using IEEE 1149.1-2013 with IEEE 1500
C.J. Clark (Intellitech Corp.)
- DFT insights for JEDEC High Bandwidth Memory (HBM)
Mike Ricchetti (AMD)
- IEEE P1149.10 High Speed JTAG - Is this the Future of SoC Test?
C.J. Clark (Intellitech Corp.)
Special Session 12C: Young Professionals in Test (Town Meeting) (Chappellet/Robert Mondavi)
Organizers: Alodeep Sanyal and Yanjing Li (Intel)
Moderator: Yervant Zorian (Synopsys)
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