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GENERAL INFO Home Committees Call for Papers Sponsors THE SYMPOSIUM Location Workshops   - WTW PRACTICAL INFO Symposium Registration Hotel reservation Travel information PROGRAM Symposium Booklet !!NEW!! Technical Program Social Event Tutorials SUBMISSIONS Types of Submissions Author Information Authors & Presenters Login Special Session Proposal IP Track Session Proposal Graduate Student Activities The TTTC Student Activities Committee is organizing two activities aiming to provide graduate students with an opportunity to disseminate their research and obtain visibility in the international test community. More... TTEP TTTC Test Technology Educational Program (TTEP) tutorials on emerging test technology topics are also offered. Tutorials VLSI Test Symposium 2009 includes an excellent TTEP 2009 tutorial on high interest test technology topic. The tutorial qualifies for IEEE TTTC certification. The tutorial will be presented on Sunday, May 3rd. The tutorial requires a separate fee and registration (see General Information). Tutorial 2: Sunday, May 3rd, 8:30am-4:30pm 7:30 - 8:30 am Tutorial Registration, Coffee Service 8:30 am - 4:30 pm Statistical Adaptive Test Methods Targeting "Zero Defect" IC Quality and Reliability PRESENTERS: ADIT SINGH (Auburn University) AUDIENCE: Test and Reliability Engineers, Engineering Managers, Reliability and Quality Assurance Managers, Researchers and Research Students DESCRIPTION: Integrated circuits have traditionally all been tested identically in the manufacturing flow. However, as the detection of subtle manufacturing flaws becomes ever more challenging and expensive in aggressively scaled nanometer technologies, innovative new statistical screening methods are being developed that attempt to improve test effectiveness and optimize test costs by adaptively subjecting "suspect" parts to more extensive testing. The idea is similar to security screening at airports. Such methods fall into two broad categories: those that exploit the statistics of defect distribution on wafers, and those that exploit the correlation in the variation of process and performance parameters on wafers. This tutorial presents test methodologies that span both these categories, and illustrates their effectiveness with results from a number of recently published experimental studies on production circuits from several companies. Sponsorship Opportunities Click here to read more about sponsorship opportunities at VTS'09. Graduate Student Activities Ph.D. students graduating in 2009 are invited to participate to the Doctoral Thesis Award Contest. All other graduate students (Ph.D. or M.S.) working on a test-related thesis are invited to participate to the Thesis Research Poster Session. Location VTS will take place from May 3rd to May 7th, 2009, in Santa Cruz, California, USA More... VTS'08 IP Presentations Presentations have been collected from VTS'08 IP sessions and are available to VTS'08 attendees. Click here for more information. DEADLINES Early Reg.: Apr. 24th, 09   CONTACTS & FEEDBACK For any questions you can contact the VTS Office, the General Chair or the Program Chair. Moreover, The VTS Organizing Committee is interested in providing a rich historical view of VTS. Please send information you believe to be relevant to the historian. For questions related to this website, please contact the Webmaster

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