2006, May 1st

07:30-09:00   Registration & coffee

09:00-10:30   Plenary Session

11:00-12:00   Sessions 1A, 1B, 1C

11:00-12:00   Session 1A - Delay Testing I

• The Impacts of Untestable Defects on Transition Fault Testing
  Xijiang LIN (Mentor Graphics Corp. - USA), Janusz RAJSKI (Mentor Graphics Corporation - USA)
• Low-cost scan-based delay testing of latch-based circuits with time borrowing
  Kun Young CHUNG (University Of Southern California - USA), Sandeep GUPTA (University Of Southern California - USA)
• Path delay fault simulation on large industrial design
  Suriyaprakash NATARAJAN (Intel Corporation - USA), Srinivas PATIL (Intel Corporation - USA), Sreejit CHAKRAVARTY (Intel Corporation - USA)

11:00-12:00   Session 1B - High Speed Interconnect Test

• A Novel Scheme for On-Chip Timing Characterization
  Ramyanshu DATTA (The University Of Texas @ Austin - USA), Gary CARPENTER (IBM Austin Research Laboratory - USA), Kevin NOWKA (IBM Austin Research Laboratory - USA), Jacob ABRAHAM (University Of Texas At Austin - USA)
• BIST for Network on Chip Interconnect Infrastructures
  Cristian GRECU (University Of British Columbia - Canada), Partha PANDE (Washington State University - USA), André IVANOV (University Of British Columbia - Canada), Res SALEH (University Of British Columbia - USA)
• Mixed PLB and Interconnect BIST for FPGAs Without Fault-Free Assumptions
  Shantanu DUTT (University Of Illinois At Chicago - USA), Vishal SUTHAR (Univ. Of Illinois At Chicago - USA)

11:00-12:00   Session 1C IP Session - Reliability Screening Methods for High-Performance Processors in Advanced Technologies

• Methods & Results for using Short Stress at Test to Reduce the need for Burn-in
  Mike TRIPP (Intel - USA)
• Analysis of SRAM Reliability: Margins, Stability, Failure Modes and Models
  Andrew TURNER (IBM - USA), Thomas BARNETT (IBM - USA)
• SRAM Latent Failure Debug and Analysis Strategy
  David EPPES (Amd - USA)

13:20-14:20    Sessions 2A, 2B, 2C

13:20-14:20   Session 2A - Heat and Power Issues in Test

• Thermal-Aware Testing of Network-on-Chip Using Multiple Clocking
  Chunsheng LIU (U Nebraska - USA)
• PEAKASO: Peak-Temperature Aware Scan-Vector Optimization
  Minsik CHO (Ut Austin - USA), David PAN (Ut Austin - USA)
• A New ATPG Method for Efficient Capture Power Reduction During Scan Testing
  Xiaoqing WEN (Kyushu Institute Of Technology - Japan), Seiji KAJIHARA (Kyushu Institute Of Technology - Japan), Kohei MIYASE (Innovation Plaza Fukuoka - Japan), Kewal SALUJA (University Of Wisconsin-madison - ), Laung-terng WANG (Syntest Technologies, Inc. - USA), Khader ABDEL-HAFEZ (Syntest Technologies, Inc. - USA), Kozo KINOSHITA (Osaka Gakuin University - Japan)

13:20-14:20   Session 2B - Test Quality

• Evaluation of Test Quality Metrics: Stuck-at, Bridge Coverage Estimation and Gate Exhaustive
  Ruifeng GUO (Intel Corp. - USA), Subhasish MITRA (Stenford - USA), Enamul AMYEEN (Intel Corporation - USA), Jinkyu LEE (University Of Texas At Austin - USA), Srihari SIVARAJ (Intel Corporation - USA), Srikanth VENKATARAMAN (Intel Corporation - USA)
• Iterative OPDD Based Signal Probability Calculation
  Avijit DUTTA (Ut Austin - USA), Nur TOUBA (University Of Texas At Austin - USA)
• Silicon Evaluation of Logic Proximity Bridge Patterns
  Sreejit CHAKRAVARTY (Intel Corporation - USA), Eric TRAN (Intel Corporation - USA), Vishwashanth KASULASRINIVAS (Intel Corporation - USA)

13:20-14:20   Session 2C IP Session - Scan Compression Techniques,Tradeoffs and Entitlement

• Design Techniques for Efficient Scan Compression
  Rubin A. PAREKHJI (Texas Instruments (india) Ltd., - India), Jais ABRAHAM (Texas Instruments (india) Pvt. Ltd, - India)
• Test Compression: Future Directions in Research, Development and Industrial Practices.
  Janusz RAJSKI (Mentor Graphics Corporation - USA), Mark KASSAB (Mentor Graphics - USA), Grzegorz MRUGALSKI (Mentor Graphics - USA), Nilanjan MUKHERJEE (Mentor Graphics - USA), Jerzy TYSZER (Poznan University Of Technology - Poland)
• Scan Compression Techniques.
  Thomas WILLIAMS (Synopsys, Inc. - USA)

14:40-15:40   Sessions 3A, 3B, 3C

14:40-15:40   Session 3A - IP protection and interconnect Testing

• Upper Bounding Fault Coverage by Structural Analysis and Signal Monitoring
  Vishwani AGRAWAL (Auburn University - USA), Soumitra BOSE (Intel Corporation - USA), Vijay GANGARAM (Intel Corporation - USA)
• A Low-Cost Solution for Protecting IPs Against Scan-Based Side-Channel Attacks
  Mohammad TEHRANIPOOR (University Of Maryland Baltimore County - USA), Jeremy LEE (University Of Maryland Baltimore County - USA), James PLUSQUELLIC (Univ. Of Maryland, Bc - USA)
• Testing the interconnects of a Network on Chip
  Khadija J STEWART (Southern Illinois University - USA), Spyros TRAGOUDAS (Southern Illinois University - USA)

14:40-15:40   Session 3B - Flash & Memory Testing

• An Overview of Failure Mechanisms in Embedded Flash Memories
  Arnaud VIRAZEL (Lirmm - France), Olivier GINEZ (Lirmm - France), Jean-michel DAGA (Atmel - France), Marylene COMBE (Atmel - France), Patrick GIRARD (Lirmm - France), Christian LANDRAULT (Lirmm - France), Serge PRAVOSSOUDOVITCH (Lirmm - France)
• A Built-In Self-Repair Scheme for NOR-Type Flash Memory
  Cheng-wen WU (National Tsing Hua University - Taiwan), Yu-ying HSIAO (National Tsing Hua University - Taiwan), Chao-hsun CHEN (National Tsing Hua University - Taiwan)
• Minimal March Test Algorithm for Detection of Linked Static Faults in Random Access Memories
  Valery VARDANIAN (Virage Logic - Armenia), Yervant ZORIAN (Virage Logic - USA), Gurgen HARUTUNYAN (Virage Logic - Armenia)

14:40-15:40   Session 3C Nanometer IC Testing---Perspectives from Foundries

• Yield, Whose Responsibility Is It?
  Cheng-ju HSIEH (Faraday Technology Corp. (a Subsidiary Of Umc) - Taiwan)
• Nanometer IC Testing---Perspectives from Chartered
  Chafik BEHIDJ (Chartered Semiconductor - Singapore)
• Nanometer IC Testing---Perspectives from TSMC
  Ann LUH (Tsmc Test Division - Taiwan)

16:00-17:00   Sessions 4A, 4B, 4C

16:00-17:00   Session 4A - Yield Analysis

• An Error-Oriented Test Methodology to Improve Yield with Error-Tolerance
  Kuen Jong LEE (National Cheng-kung Univ - Taiwan), Tong-yu HSIEH (National Cheng Kung University - Taiwan), Melvin BREUER (University Of Southern California - USA)
• Early, Accurate and Fast Yield Estimation through Monte Carlo-Alternative Probabilistic Behavioral Analog System Simulations
  Rasit TOPALOGLU (University Of California San Diego - USA)
• BIST Pretest of ICs: Risks and Benefits
  Yoshiyuki NAKAMURA (Nec Electronics Corp. - Japan), Jacob SAVIR (New Jersey Institute Of Technology - USA), Hideo FUJIWARA (Nara Institute Of Science And Technology - Japan)

16:00-17:00   Session 4B - New Topic: Emerging Nanoelectronic Devices for High Speed, Low Power Application

• Organizer: Bernard COURTOIS (TIMA-France)
  Presenter: Sumann DATTA (Inter Corporation - USA)

16:00-17:00   Session 4C IP Session: TRP in Action - Embedded Instrumentation in FPGAs

• Embedded FPGA Logic Analyzer
  Bertrand LEIGH (Lattice Semiconductors - USA)
• Shrinking Debug Cycles by Exploiting Design Observability
  Oliver TAN (Altera Corporation - USA)
• Shorten System Level Test Times using Xilinx ChipScope On-Chip Verification Solutions
  Przybus BRENT (Xilinx Corporation - USA)

20:00-21:30   Sessions 5A, 5B, 5C

20:00-21:30   Session 5A: Special Session

• TBD
  

20:00-21:30   Session 5B: Elevator Talk Session

• Organizer: Erik CHMELAR (LSI Logic - USA)
  Moderator: Prof. Edward J. MCCLUSKEY (Stanford University - USA)

20:00-21:30   Session 5C: Embedded Tutorial: Functional ATPG

• Organizer: Praveen PARVATHALA (Intel Corporation - USA)
  Presenters:
  Jacob ABRAHAM (University of Texas at Austin - USA)
  Rajesh GALIVANCHE (Intel Corporation - USA)
  Rajesh RAINA (Freescale Semiconductor - USA)

2006, May 2nd

08:30-09:30   Sessions 6A, 6B, 6C

08:30-09:30   Session 6A - Test Generation and Test Flows

• Improved Handling of False and Multicycle Paths in ATPG
  Bruce SWANSON (Mentor Graphics - USA), Vlado VORISEK (Freescale Semiconductor - USA), Dhiraj GOSWAMI (Mentor Graphics - USA)
• On the Automation of the Test Flow of Complex SOCs
  Michelangelo GROSSO (Politecnico Di Torino - Italy), Davide APPELLO (Stmicroelectronics - Italy), Vincenzo TANCORRE (Stmicroelectronics - Italy), Matteo SONZA REORDA (Politecnico Di Torino - Italy), Maurizio REBAUDENGO (Politecnico Di Torino - Italy), Paolo BERNARDI (Politecnico Di Torino - Italy)
• Improving Gate-Level ATPG by Traversing Concurrent EFSMs
  Graziano PRAVADELLI (University Of Verona - Italy), Franco FUMMI (Università Di Verona - Italy), Cristina MARCONCINI (Università Di Verona - Italy), Giuseppe DI GUGLIELMO (University Of Verona - Italy)

08:30-09:30   Session 6B - IDDQ, MEMS, and Wireless Testing

• X-IDDQ: A Novel Defect Detection Technique using IDDQ Data
  Anura P. JAYASUMANA (Colorado State Univ. - USA), Ashutosh SHARMA (Colorado State University - USA), Yashwant MALAIYA (Colorado State University - USA)
• Energy Reduced Software-Based Self-Testing for Wireless Sensor Network Nodes
  Zeljko ZILIC (Mcgill University - Canada), Rong ZHANG (Mcgill University - Canada), Katarzyna RADECKA (Mcgill University - Canada)
• Built-In Test and Self Calibration of MEMS Accelerometer Sensors
  Vishwanath NATARAJAN (Georgia Institute Of Technology - USA), Soumendu BHATTACHARYA (Georgia Institute Of Technology - USA), Abhijit CHATTERJEE (Georgia Institute Of Technology - USA)

08:30-09:30   Session 6C IP Session - Test Strategies of Leading Edge SoCs

• The Application and Enhancement of Test Cost Reduction Method for SoCs
  Takahisa HIRAIDE (Fujitsu Laboratories Ltd - Japan), Tatsuru MATSUO (Fujitsu Laboratories Ltd - Japan), Hideaki KONISHI (Fujitsu Ltd - Japan), Michiaki EMORI (Fujitsu Ltd - Japan), Takashi AIKYO (Fujitsu Ltd - Japan), Masayuki ARAI (Tokyo Metropolitan University - Japan), Satoshi FUKUMOTO (Tokyo Metropolitan University - Japan), Kazuhiko IWASAKI (Tokyo Metropolitan University - Japan)
• Failure and Critical-Path Analysis Using Logic BIST
  Naoki KIRYU (Toshiba Corp. - Japan)
• Strategies for Reducing Test Cost of SoCs
  Michinobu NAKAO (Renesas Technology Corp - Japan), Hiroki WADA (Renesas Technology Corp - Japan), Kazumi HATAYAMA (Renesas Technology Corp. - Japan), Hiroyuki ADACHI (Renesas Technology Corp - Japan)

09:50-10:50   Sessions 7A, 7B, 7C

09:50-10:50   Session 7A - Designing Robust CMOS and Nanoelectronics

• Design optimization for robustness to soft errors
  Kartik MOHANRAM (Rice University - USA), Quming ZHOU (Rice University - USA), Mihir CHOUDHURY (Rice University - USA)
• Design of Soft-Error Resilient Linear Digital Filters Using Low-Cost Checksum-Based Probabilistic Error Correction
  Maryam ASHOUEI (Georgia Tech. - USA), Soumendu BHATTACHARYA (Georgia Institute Of Technology - USA), Abhijit CHATTERJEE (Georgia Institute Of Technology - USA)
• Reconfigurable Nanofabric Designs for Online Fault Masking through Dynamic Redundancy Adaptation
  Wenjing RAO (Ucsd Cse Dept - USA), Alex ORAILOGLU (University Of California At San Diego - USA), Ramesh KARRI (Polytechnic University - USA)

09:50-10:50   Session 7B - RF Testing

• Low Cost Wafer Level Alternate Diagnosis of RF paths on Modern Wireless Transceivers using Loop-back DfT Approach
  Ganesh SRINIVASAN (Georgia Institute Of Technology - USA), Friedrich TAENZLER (Texas Instruments - USA), Abhijit CHATTERJEE (Georgia Institute Of Technology - USA)
• RF Front-end System Gain and Linearity Built-in Test
  Qi WANG (University Of Washington - USA), Mani SOMA (Univ. Of Washington - USA)
• Integrated CMOS Power Sensors for RF BIST Applications
  Liang-hung LU (National Taiwan University - Taiwan), Hsieh-hung HSIEH (National Taiwan University - Taiwan)

09:50-10:50   Session 7C - IP Session - High Test Parallelism, Throughput and Quality at a Low Cost: Which Test Cells and Which Partitioning of Test Resources Can Enable All This?

• Achieving Full Spectrum Coverage Exploiting Advanced Contacting Technologies
  Bruce BARBARA (Formfactor - USA)
• Test Resource Partitioning practices for test time optimization at the SOC level
  Yervant ZORIAN (Virage Logic - USA)
• New Frontiers with the Convergence of Low-Cost Testing and DFT Technology: merging Burn-In with B/E and F/E test
  Vincenzo MIGLIORATI (Eles Semiconductor Equipment - Italy)

11:10-12:10   Sessions 8A, 8B, 8C

11:10-12:10   Session 8A - Test Size Reductions

• Modular compactor of test responses
  Wojtek RAJSKI (Oregon State University - USA), Janusz RAJSKI (Mentor Graphics Corporation - USA)
• Combining Linear and Non-Linear Test Data Compression using Correlation-Based Rectangular Encoding
  Jinkyu LEE (University Of Texas At Austin - USA), Nur TOUBA (University Of Texas At Austin - USA)
• Efficient Fault Collapsing via Generalized Dominance Relations
  Vishnu VIMJAM (Virginia Tech - USA), Michael HSIAO (Virginia Tech - USA)

11:10-12:10   Session 8B - Transistor Level Diagnosis

• A gate level method for transistor level bridging fault diagnosis
  Xinyue FAN (Oxford University - United Kingdom), Will MOORE (Oxford University - United Kingdom), Camelia HORA (Philips - Netherlands), Mario KONIJNENBURG (Philips - Netherlands), Guido GRONTHOUD (Philips - Netherlands)
• Parametric Fault Diagnosis for Analog Circuits Using a Bayesian Framework
  Fang LIU (Duke University - USA), Plamen NIKOLOV (Duke University - USA), Sule OZEV (Duke University - USA)
• Decision Tree based Mismatch Diagnosis in Analog Circuits
  Mingjing CHEN (University Of California, San Diego - USA), Alex ORAILOGLU (University Of California At San Diego - USA)

11:10-12:10   Session 8C - IP Session - Soft Error Impact on Modern Systems

• Why you must and how you can evaluate the impact of soft errors on the reliability of your SoC
  Olivier LAUZERAL (Iroc Technologies - France)
• SEU Impact on Reliable System.
  Sung Soo CHUNG (Cisco - USA)
• Impact of soft errors on the Reliability and Availability of servers designed for the Internet computing era.
  Ishwar PARULKAR (Sun Microsystem - USA)

13:45-15:15   Sessions 9A, 9B, 9C

13:45-15:15   Session 9A - Panel Session: Real-Time Volume Diagnostics: Requirements and Challenges

• Organizers: Ajay KHOCHE (Semiconductor Test Solutions, Agilent Technologies - USA)

13:45-15:15   Session 9B - Special Session: Doctoral Thesis Award

• Organizer: Andreas VENERIS (University of Toronto - Canada)
  Moderator: Yiorgos MAKRIS (Yale University - USA)

13:45-15:15   Session 9C - Panel Session: Three Questions to Oracle

• Organizers: Kee Sup KIM (Intel - USA), Mohammad TEHRANIPOOR (University of Maryland Baltimore County - USA)
  Presenters:
  Janak PATEL (University of Illinois - USA)
  Al CROUCH (Innovys - USA)
  Ken BUTLER (Texas Instruments - USA)
  Anne GATTIKER (IBM - USA)
  Subhasish MITRA (Stanford University - USA)
  Sule OZEV (Duke University - USA)

15:30-23:00   VTS 2006 Social Program

2006, May 3rd

09:00-10:00   Sessions 10A, 10B, 10C

09:00-10:00   Session 10A - Delay Testing II

• A Test Generation Procedure for Avoiding the Detection of Functionally Redundant Transition Faults
  Hangkyu LEE (Purdue University - USA), Sudhakar REDDY (University Of Iowa - USA)
• Robust Tests Generation for Precise Crosstalk-induced Path Delay Faults
  Huawei LI (Institute Of Computing Technology, Cas - China), Peifu SHEN (Institute Of Computing Technology, Chinese Academy Of Sciences - China), Xiaowei LI (Ict, Cas - China)
• Multi-Cycle Sensitizable Transition Delay Faults
  Jais ABRAHAM (Texas Instruments (india) Pvt. Ltd, - India), Arun KUMAR (Texas Instruments (india) Pvt. Ltd. - India), Uday GOEL (Indian Institute Of Technology, New Delhi - India)

09:00-10:00   Session 10B - Analog Test

• A Signal to Noise Ratio BIST for Sigma-Delta Analogue-to-Digital Converters
  Luis ROLINDEZ (Tima Laboratory - Stmicroelectronics - France), Salvador MIR (Tima Laboratory - France), Ahcène BOUNCEUR (Tima Laboratory - France), Jean-louis CARBONERO (Stmicroelectronics - France)
• Investigating the Efficiency of Integrator-Based Capacitor Array Testing Techniques
  Haibo WANG (Southern Illinois University - USA), Sai DURBHA (Southern Illinois University - USA), Amit LAKNAUR (Southern Illinois University - USA)
• Functional Test of Field Programmable Analog Arrays
  Tiago BALEN (Ufrgs - Brazil), Marcelo LUBASZEWSKI (Federal University Of Rio Grande Do Sul (ufrgs) - Brazil), Jose Vicente CALVANO (Brazilian Navy Research Institute - Brazil), Michel RENOVELL (Lirmm - France)

09:00-10:00   Session 10C - IP Session - System-in-Package Design and Test Practices

• System-in-Package Test: Problems, Practices and Solutions
  Davide APPELLO (Stmicroelectronics - Italy)
• Schematic Based Chip/Package Co-design Flow for Mixed-Signal System-in-Package Designs
  Thomas BRANDTNER (Infineon - Austria)
• SoC Integration - SIP vs. SOC vs. POP
  Peter RICKERT (Texas Instruments - USA)

10:20-11:20   Sessions 11A, 11B, 11C

10:20-11:20   Session 11A - Delay Testing III

• Enhanced Timing-Based Transition Delay Testing for Small Delay Defects
  Richard PUTMAN (Cirrus Logic - USA), Rahul GAWDE (Cirrus Logic - USA)
• Scan Tests with Multiple Fault Activation Cycles for Delay Faults
  Sudhakar REDDY (University Of Iowa - USA), Zhuo ZHANG (University Of Iowa - USA), Xijiang LIN (Mentor Graphics Corp. - USA), Janusz RAJSKI (Mentor Graphics Corporation - USA)
• Output Hazard-Free Transition Tests for Silicon Calibrated Scan Based Delay Testing
  Gefu XU (Auburn University - USA), Adit SINGH (Auburn University - USA)

10:20-11:20   Session 11B - Nanoscale Testing

• Low Vdd vs. Delay: is it really a good correlation metric for nanometer ICs?
  Sebastian BOTA (Universitat De Les Illes Balears - Spain), Marcos ROSALES (Universitat De Les Illes Balears - Spain), Josep ROSSELLO (Universitat De Les Illes Balears - Spain), Jaume SEGURA (Univ. De Les Illes Balears - Spain)
• Exploiting Regularity for Inductive Fault Analysis
  Jason G BROWN (Carnegie Mellon - USA), Shawn BLANTON (Carnegie Mellon - USA)
• SCT: An Approach for Testing and Configuring Nanoscale Devices
  Mohammad TEHRANIPOOR (University Of Maryland Baltimore County - USA), Reza RAD (University Of Maryland Baltimore County - USA)

10:20-11:20   Session 11C - IP Session - Impact of Variations on Design and Test

• Process Variation Impacts on ASIC Timing and Leakage
  Paul ZUCHOWSKI (IBM - USA)
• Process Variation in Nanometer ASICs and SoCs: Problems, Implications, and Solutions
  Rich LAUBHAN (Lsi Logic - USA)
• Testing a Moving Target: Validation of an Adaptive Microprocessor
  Eric FETZER (Intel - USA)

11:40-12:40   Sessions 12A, 12B, 12C

11:40-12:40   Session 12A - Scan Based Diagnosis

• Accelerating Diagnostic Fault Simulation using Z-diagnosis and Concurrent Equivalence Identification
  Bharath SESHADRI (Purdue University - USA), Xiaoming YU (Intel Corporation - USA), Srikanth VENKATARAMAN (Intel Corporation - USA), Sudhakar REDDY (University Of Iowa - USA)
• A pattern ordering algorithm for reducing the size of fault dictionaries
  Paolo BERNARDI (Politecnico Di Torino - Italy), Matteo SONZA REORDA (Politecnico Di Torino - Italy), Maurizio REBAUDENGO (Politecnico Di Torino - Italy), Michelangelo GROSSO (Politecnico Di Torino - Italy)
• Dominance Based Analysis for Large Volume Production Fail Diagnosis
  Bharath SESHADRI (Purdue University - USA), Srikanth VENKATARAMAN (Intel Corporation - USA)

11:40-12:40   Session 12B - Mixed Signal Test

• A Period Tracking Based On-Chip Sinusoidal Jitter Extraction Technique
  Jiun Lang HUANG (National Taiwan University - Taiwan), Chia-yuan KUO (National Taiwan University - Taiwan)
• Bridging the Accuracy of Functional and Machine-Learning-Based Mixed-Signal Testing
  Yiorgos MAKRIS (Yale University - USA), Haralampos-g STRATIGOPOULOS (Yale University - USA)
• Prediction for Specification-Based Loopback Test of Embedded Mixed-Signal Circuits
  Hongjoong SHIN (The University Of Texas At Austin - USA), Byoungho KIM (The University Of Texas At Austin - USA), Jacob ABRAHAM (University Of Texas At Austin - USA)

11:40-12:40   Session 12C - IP Session - Making the (Yield) Difference: DFY/DFM

• Design planning and techniques for yield improvement
  Jun QIAN (Cisco - USA)
• Yes, Virginia, there is EDA in DFM/DFY
  Marc LEVITT (Cadence Design - USA)

14:00-15:30   Sessions 13A, 13B, 13C

14:00-15:30   Session 13A - Embedded Tutorial: Silicon Debug Challenges for Nanometer Designs

• Organizer: Rajesh GALIVANCHE (Intel Corporation - USA)
  Moderator: Bob GOTTLIEB (Intel Corporation - USA)
  Presenters:
  Miron ABRAMOVICI, (DAFCA - USA)
  Jeff REARICK (Agilent Technologies - USA)
  Jason STINSON (Intel Corporation - USA)
  Bart VERMEULEN (Philips Research - Netherlands)

14:00-15:30   Session 13B - Hot Topic Session: Signal Integrity: How Can It be Designed Into Multiprocessor Platforms, Systems On-Chip, and Systems in-Package?

• Organizer: André IVANOV (University of British Columbia, Canada)
  Presenter:
  T.M. Mak (Intel - USA)
  M. Coppola (ST Microelectronics - Italy)
  P. Pande (Washington State University - USA)

14:00-15:30   Session 13C - Panel Session: Changing Role of Test: Is ATE Ready?

• Organizers: Ajay KHOVHE (Semiconductor Test Solutions, Agilent Technologies - USA), Mike Rodgers (Intel Corporation - USA)
  Moderator: Pete O'NEILL (Avago Technologies - USA)
  Presenters:
  Uli SCHOETTMER (Agilent Technologies Inc. - Germany)
  Rochit RAJSUMAN (Advantest Corporation - USA)
  Lee SONG (Teradyne Inc. - USA)
  Burnie WEST (Credence Corporation - USA)
  Dan GLOTTER (OptimalTest - USA)
  Bill PRICE (Philips Semiconductors - USA)