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The IEEE VLSI Test Symposium (VTS) explores emerging trends and novel concepts in test, validation, yield, reliability, and security of microelectronic circuits and systems.

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The symposium will take place on April 27-29 2026, in Napa, CA, USA.

The program includes keynotes, scientific paper presentations, late breaking result papers, short industrial application paper presentations, special sessions, and Innovative Practices sessions.

For more information about the call for papers and the submissions, please visit our Author information page.

Click the button below to download the latest call for papers:

CFP_VTS2026 (3532 downloads )

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You are invited to participate and submit your contributions to VTS’26. The areas of interest include (but are not limited to) the following topics:

VTS Topics

Generative AI Applications in Test and Security Silicon Lifecycle Management Silent Data Corruption Test-Enabled Digital Twin Analog – Mixed-Signal – RF Test ATPG and Compression Automotive Test and Safety Built-In Self-Test (BIST) Functional safety Digital twin-enabled test and security High BW Test through High-Speed Interfaces Testing for extreme environments Test og Non-Si and Compound Circuits Test and Security of Quantum Circuits Test and Security of Photonic Circuits Test and Security of Emerging Memory Technologies Functional Debug through Scan Fault Modeling and Simulation Low-Power IC Test

Machine Learning for Test and Security Microsystems/MEMS/Sensors Test Memory Test and Repair Test for 3D and Heterogenous Integration Yield Optimization Online Test and Error Correction Power and Thermal Issues in Test System-on-Chip (SOC) Test Test and Reliability of Biomedical Devices Test and Reliability of High-Speed I/O Test and Security of Machine Learning Hardware Test Standards FPGA Test Defect-Based Test Defect and Fault Tolerance Delay and Performance Test Design for Testability Post-silicon Validation and Debug Hardware Security Embedded System and Board Test